Insulated gate field effect transistors (IGFETs), and the subclass of metal-oxide-semiconductor (MOS) FETs are well-known in the art of designing and fabricating integrated circuits. For example, FIG. 2 illustrates a prior art n-channel MOS transistor 10 in a p.sup.- semiconductor substrate 12 having n.sup.+ source/drain regions 14 and 16, covered by a thin gate dielectric layer 18 upon which rests a gate 20 of conductive material. The channel under the gate 20 between the source and drain 14 and 16 has a length, L, that the carriers travel between the source and drain regions 14 and 16. The field effect transistor 10 of FIG. 2 has a significant disadvantage in that the threshold voltage, V.sub.T, usually varies with respect to geometry, the channel length L measured in the direction X, and the drain bias.
For long channel field effect devices, the device can be designed so that this problem can be minimized or ignored. However, as L decreases, there is a considerable problem with a diminishing V.sub.T, such as in seen schematically in curve A of FIG. 3. For a longer length L.sub.1, V.sub.T is fairly well-behaved and constant. However, as L decreases to L.sub.2, with conventional devices the V.sub.T drops off appreciably. This effect severely impairs device performance and makes it difficult to design integrated circuits with these short channel lengths. If the curve could be moved out as shown in curve B, then the V.sub.T would not fall off as soon, and the detrimental short channel effects would be alleviated.
Ideally, the V.sub.T vs. L curve should appear more like curve B, that is, flatter for a greater L range, so that V.sub.T remains fairly constant even for very short channel lengths. This depletion layer shape affects the V.sub.T as well. Thus, it would be advantageous to have a field effect or MOS device with a minimum of V.sub.T variation with respect to channel length and the drain bias. It has recently been discovered, by the inventor herein as disclosed in this application, that such devices may be provided by having a FET employing a semiconductor material gate where portions of the gate are doped with impurities of the two different conductivity types. For example, in a specific embodiment, the central portion of a polycrystalline silicon gate may be doped n.sup.+ conductivity type and the ends of the gate may be doped p.sup.- and p.sup.+ conductivity type.
The only publication known which reveals the use of insulated gate field effect transistors having gates of more than one conductivity type electrically connected is U.S. Pat. No. 4,559,694 to Yoh, et al. This patent concerns a method of manufacturing a reference voltage generator device. The gates of the IGFETs have central portions and end portions where the conductivity types of the end portions and the central portions are different. Sometimes the end portions and the central portions of the gate were separated by a portion of intrinsic semiconductor material. However, in all cases described in the patent, the impurity level of the end portions of the gate electrode was the same as the impurity level of the source/drain regions on either side of the entire gate, for they were formed in the same step. Therefore, of course, in all instances the conductivity type of the gate end portions and the source/drain regions are the same. Although channel length dimensions are not mentioned in U.S. Pat. No. 4,559,694, it is expected that they would be considerably longer that those of concern in the present invention to be able to form the voltage reference funtions required.
This characteristic is important because the problems with threshold voltage control discussed above are not apparent until the channel length approaches submicron levels. Of course, the minimum channel length, L, for any particular device, depends on the channel doping level and the gate oxide thickness. Nevertheless, it is expected that only devices with channel lengths longer than about 5 um could be made with the method of U.S. Pat. No. 4,559,694. The fabrication methods taught therein are completely incompatible with devices having channel lengths in the micron to submicron realm, and rely heavily on photolithographic resolution. It is generally recognized that photolithographic resolution techniques reach their limits at about one micron.
It would be advantageous if a method could be discovered for fabricating FETs with semiconductor material gates where different portions of the gates have different conductivity types, and where techniques other than photolithographic techniques are employed for resolving the different portions of the gates.